Co-Synthesis of Instruction Sets and Microarchitectures

The design of an instruction set processor includes several related design tasks: instruction set design, microarchitecture design, and code generation. Although there have been automatic approaches for each individual task, the investigation of the interaction between these tasks still primarily relies on designers’ experience and ingenuity. It is thus the goal of this research to develop formal models and algorithms to investigate such interaction systematically. This dissertation presents a two-phase co-synthesis approach to the problem. In the architectural level, given a set of application benchmarks and a pipeline structure, the ASIA (Automatic Synthesis of Instruction set Architecture) design automation system generates an instruction set and allocates hardware resources which best fit the applications, and, at the same time, maps the applications to assembly code with the synthesized instruction set. This approach formulates the codesign problem as a modified scheduling/allocation problem. A simulated annealing algorithm is used to solve the problem. Following ASIA, the microarchitectural-level design automation system PIPER accepts the instruction set architecture specification and generates a pipelined microarchitecture which implements the instruction set, and a reordering table which guides the compiler backend (reorderer). This approach relies on an extended taxonomy of inter-instruction dependencies and the associated hardware/software resolutions. The techniques are demonstrated with both illustrative and practical experiments. The results show that the techniques are capable of synthesizing instruction set processors that are as good as or better than the manually-designed instruction set architecture VLSI-BAM in application-specific environments, based on a design metric consisting of the instruction set size, cycle count and hardware resources. In addition, these techniques can be used to characterize architectural properties of application benchmarks. CO-SYNTHESIS OF INSTRUCTION SETS AND MICROARCHITECTURES